Frame Engineering Intern (Jan-Jun 2027)

About GlobalFoundries

GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers differentiated, power-efficient and high-performance solutions for high-growth markets. With global manufacturing operations across the U.S., Europe, and Asia, GF is a trusted and holistic technology partner for customers worldwide. GF’s talented global team remains focused every day on security, longevity, and sustainability. For more information, visit www.gf.com.

Internship Program Overview

Our Interns & Co-ops are the entry-level talent pipeline for GF across the globe. Our goal is to provide students with a meaningful work experience that equips them with the skills to embark on a career in the fast-paced and growing semiconductor industry after graduation. As an intern at GF, you’ll experience one-on-one mentorship, work assignments that prioritize your growth and potential, professional development opportunities, and the chance to network with executives.

Summary of Role

GlobalFoundries is looking for a highly motivated individual to work in the Tape out organization as an Intern Frame Engineering located in Singapore. The successful candidate will support tape out operations activities ranging from frame design for a range of technologies to process improvements for enhanced productivity and quality.

This role requires working with worldwide Frame and other engineers who use semiconductor manufacturing tools (i.e., lithography and metrology) and test tools in our fabs. You will engage in continuous process improvement in the increasingly complex world of chip manufacturing by applying Failure Mode and Effect Analysis, structured problem-solving, and driving actions to reduce risks.

Essential Responsibilities & Project May Include

• Engage in daily operations activities, including facilitating technology frame requirements, frame structures layout and frame generation for chips, ad-hoc change execution, work queue prioritization, and work hand-off across geographic locations.
• Use or customize internally developed software tools and commercially available software tools to enhance design process productivity (including generating input files that drive automation for fabs and Mask House).
• Make decisions to hold, escalate, promote, and reject tape out support issues in alignment with FAB, Tape out Logistics Integration, and FAEs.
• Interact with other teams such as Application Engineering, Product Engineering, Release Team, and Design Enablement to provide a best-in-class Customer Tape-out Operations experience.
• Close collaboration with the FAB and TD team to provide solutions that improve efficiency, reduce costs, and improve cycle time.
• Participate in assessing team business processes and suggest continuous improvements and automation opportunities to enhance productivity.
• Ensure processes are well documented, failure modes are assessed, and mitigation and detection are in place.

What You’ll Gain

• Hands-on exposure at a semiconductor manufacturing company, shadowing experts and supporting real production work.
• A working understanding of the wafer fabrication process and your assigned process module.
• Roundtable sessions with local leadership and cross-department networking opportunities.
• A capstone presentation at the end of the internship covering your project results, learnings, and recommendations for improvement.

Other Responsibilities

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications

• Education: Actively pursuing a Bachelor’s degree in Chemical Engineering, Electrical/Electronic Engineering, Mechanical Engineering, or Physics (or related field) through an accredited degree program during the time of internship.
• Working knowledge of Unix shells, with interest/aptitude to learn domain-specific programming/scripting languages and data formats.
• Experience with the Virtuoso environment and SKILL programming.
• Must be in good academic standing.
• Ability to work at least 40 hours per week during the internship.
• Available for a 16–24 week credit-bearing internship commencing January 2027.

Preferred Qualifications

• Prior related internship or co-op experience.
• Device Layout knowledge/experience (plus).
• Experience with Cadence Mask Compose (big plus).
• An inquisitive mindset and a positive, proactive learning attitude.

Additional Application Information

Please indicate your internship period clearly in your CV/resume/cover letter.