GPU Internships - RTL Design, RTL Power Optimisation & Physical Design

GPU Internship (RTL Design, RTL Power Optimisation, and Physical Design) — UK

Apple’s UK GPU team works on IPs that are part of Apple’s world-class GPU designs for Apple Silicon SoCs. We are seeking highly motivated, innovative, and confident individuals to join us across the following areas: RTL Design, RTL Power Optimisation, and Physical Design.

As a member of the chip design effort, you will work with multiple disciplines and have a critical impact on delivering high-performance products efficiently to millions of Apple customers.

Locations

• London (Bishopsgate)
• St Albans
• Cambridge

You may express your location preferences if selected for interview.

Start Dates

• Winter 2026
• Spring / Summer 2027

Key Dates

• Applications close: mid-October
• Initial interviews: October
• Final round interviews: November

Internship Roles

RTL Design

• Assist with delivering high-quality IP to meet performance, feature, timing, area, and power goals.
• Collaborate with Design Engineers and work alongside platform architecture, functional verification, and physical design teams responsible for GPU products.
• Balance energy efficiency and area constraints with project schedule and maintainability.

RTL Power Optimisation

• Dive into power estimation and optimisation for next-generation silicon designs.
• Analyse and optimise power take-down strategies.
• Set targets for future IP.
• Generate power data to support critical decisions.
• Innovate and improve methodologies for power data extraction and reporting to enhance efficiency and performance.
• Collaborate with experienced engineers to expand technical expertise in silicon hardware.

Physical Design

• Join the GPU physical design (PD) team working on physical design for new Apple products.
• Learn how a modern ASIC design flow works, including floorplanning, placement, and routing.
• With mentorship, identify metrics, analyse results, and help write scripts to automate flows and improve key metrics.
• Utilise the latest technologies and learn from experienced engineers.
• Partner with RTL Design teams to understand chip architecture and how physical design interfaces with RTL to achieve strong results.

Minimum Qualifications

• Currently pursuing a BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field.
• At the end of the internship, you must return to school to continue your education, or the internship must be the last requirement for you to graduate.
• Curiosity about GPU/CPU architecture and micro-architecture.
• Strong coding skills with C or C++ for internships in RTL Design and RTL Power Optimisation.
• Knowledge of scripting languages such as Perl, Python, or Ruby.
• Familiarity with SystemVerilog / Verilog / VHDL.

Preferred Qualifications

• Strong interpersonal and analytical skills.
• Ability to work well in a team and remain productive under tight schedules.
• Understanding of STA (Static Timing Analysis) and Synthesis for an internship in Physical Design.