[2027 Internship] Physical Verification Software CAD Intern

Overview

When you join us, you will work alongside experienced engineers who will mentor and guide you.

Responsibilities

• Execute design rule checks on real chip designs.
• Debug real issues related to design rule checks during full chip integration.
• Perform basic reporting on physical verification issues.
• Support basic project management and project risk assessment reporting.
• Build basic scripting automation.

Learning Outcomes

• Become familiar with the Linux environment.
• Develop deep knowledge of Physical Verification in chip tape-out operations.
• Understand and gain exposure to the full-chip construction process, including:
  • Building from individual IPs (IO/Analog/Digital)
  • Creating necessary physical structures (e.g., seal ring, mask alignment markers, clamp cells)
  • Dummy generation
• Gain hands-on experience with layout tools (e.g., Synopsys Laker).
• Gain hands-on experience executing design rule checks (e.g., Mentor Graphics Calibre).
• Gain hands-on debugging experience for real chip issues related to physical verification.
• Develop experience with basic project management.
• Experience the dynamics of backend closure for a real product tape-out.
• Gain hands-on experience in scripting using Tcl/Python/Csh.
• Learn real dynamics in cross-team collaboration.