# IC Design Exploration Intern [AMD](https://www.jorb.ai/firms/amd.md) · Singapore · [Electrical Engineering](https://www.jorb.ai/jobs/electrical-engineering.md) AMD is hiring a IC Design Exploration Intern in Singapore. Posted 2026-07-28; applications close 2026-09-26. **Apply**: https://careers.amd.com/careers-home/jobs/76892 Posted 21h ago. ## Role details ## Intern - IC Design Exploration (IC Design) As an AMD **intern/co-op**, you’ll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You’ll do important work, learn new skills, expand your network, and gain real-world experience on projects that impact millions of end-users worldwide. **Location:** Singapore **Criteria:** Current students studying in universities based in Singapore **Internship Duration:** Begins on either **4 May 2026** or **20 July 2026**, and ends on **4 Dec 2026**. Option to extend the internship, with the extended period concluding on **18 Dec 2026**. ## What You Can Expect to Learn - Gain industry experience working on the latest technology process nodes. - Learn how fulfilling a career in IC design can be. - Because IC design includes various disciplines, you’ll be assessed during the application process and assigned to the most suitable team. ## Project Overview Jump start your IC design journey as part of a dynamic team covering many areas, including but not limited to analog design and implementation, digital design and implementation, functional verification, post-silicon validation, and more. You will be part of the SerDes Technology team and will collaborate with teams around the globe. Working alongside engineers across different disciplines will help you understand how disciplines differ, so you can make an informed decision about your path after graduation. ## Key Responsibilities - **First few weeks** - Get to know more about the Singapore Design Team at AMD. - Strengthen foundational technical IC design knowledge. - Get comfortable working independently as well as in a team environment across multiple geographical sites. - **Next few months** - Develop soft skills such as communication and presentation by participating in technical discussions and conducting knowledge-sharing sessions. - Appreciate the considerations involved in engineering judgment decisions. - Work on projects as part of specialization (details below). - **Throughout the internship** - Participate in company/department events, social events, recreation events, and related activities. ## Specializations (Assigned to One) - **Analog design** - Design and develop high-speed analog and mixed-signal circuit and auxiliary circuit block design (112Gbps and above) in advanced technology nodes (3nm, 7nm). - Use, simulate, and analyze logs/reports generated from EDA tools, and make design trade-offs to achieve results within scheduled milestones. - Learn the architecture and design of SERDES blocks (transmitter, receiver, PLL, etc.). - Basic scripting and programming (Unix, Python, Perl). - Familiarize with IC design tools (Cadence ADE/Spectre, Synopsys Hspice/XA, etc.). - Learn and understand IC design flow to implement circuit design. - Opportunity to explore cross-functional experience (e.g., RTL/Layout/STA/Verification). - **Analog layout implementation** - Implement layout for high-speed circuits and auxiliary circuit block design (112Gbps and above) in advanced technology nodes (3nm, 7nm). - Perform physical verification checks such as Layout-versus-Schematic (LVS) and Design Rule Check (DRC) to meet circuit function, performance, and process requirements. - Understand basic process design rules and differences in metal schemes. - Basic scripting and programming (Unix, Python, Perl). - Familiarize with IC design tools (Cadence Virtuoso, Calibre, etc.). - Learn and understand IC design flow to implement layout design. - Opportunity to explore cross-functional experience (e.g., RTL/Circuit/PnR/STA/Verification). - **Analog static timing analysis** - Develop timing models for advanced technology nodes for mixed-signal circuits and complex standard cells. - To enable a good static timing analysis run, work with stakeholders (design, layout, and integration teams) to build constraints, tune design hierarchy level, and review timing reports to generate timing models. - Ensure the quality of generated models by developing and updating quality-check scripts. - Release and maintain timing model databases. - Evaluate best-in-class EDA tools and flows in the industry. - **Digital design** - **Roles** - **Digital Design** - Low Power design explorations. - Design digital logic blocks in Verilog (RTL). - Develop testbenches and perform functional verification of developed digital logic blocks. - **Silicon validation** - Develop an emulation platform using Python and cocotb (https://www.cocotb.org/). - Post-silicon validation, testing, and debug of block functionality on prototype silicon. - **Next generation RTL/AI tool** - Explore new approaches to improve RTL quality and productivity. - Explore AI/ML to improve RTL methodology. - **Preferred skills** - Good fundamentals of digital logic design. - Experience in Verilog and/or VHDL. - Good programming/scripting skills (Python, OOP concepts, Perl, etc.). - **Digital implementation** - Work proficiently in UNIX/Linux environments to use EDA tools such as Synopsys Design Compiler, IC Compiler 2, and Fusion Compiler. - Implement P&R designs using the latest technology from 3nm to 16nm process nodes. - Develop and implement plans to synthesize and close timing on complex digital integrated circuits at the block, subsystem, or device level (100K to 10M+ gates) coded in VHDL/Verilog. - Design complex clock structures to meet tight skew requirements. - Collaborate with design groups across disciplines (Logic, Circuits, DFT & Layout) to meet timing closure, area, power, and performance requirements. - Ensure the implemented design meets required DRC for process nodes below 16nm as well as DFM. - Communicate regularly with project teams worldwide to resolve issues and ensure targeted goals and schedule are met. - **Digital static timing analysis** - Work proficiently in UNIX/Linux environments to use EDA tools such as Synopsys PrimeTime. - Develop timing constraints to enable static timing analysis. - Simulate and analyze logs/reports generated from EDA tools (mainly ICC2 and PrimeTime), and make design trade-offs to achieve required results within scheduled milestones. - **Functional verification** - **Roles** - **Functional verification of SerDes and/or Security IP design blocks** - Participate in testbench environment design and implementation in SystemVerilog/UVM-based framework and/or Python-based framework. - Execute and manage regressions; work closely with the design team to debug, identify, and resolve design bugs. - Perform coverage analysis to ensure all design features are verified. - **Simulation framework development** - Participate in development of automation and/or hardware acceleration to improve engineering efficiency and productivity. - Participate in exploration of incorporating AI/ML into the automation framework. - **Next generation verification methodology exploration** - Participate in exploration of new approaches to improve verification quality and productivity. - Participate in exploration of incorporating AI/ML into verification methodologies. - **Preferred skills** - Good fundamentals of digital logic design. - Experience in SystemVerilog and/or UVM. - Good programming/scripting skills (Python, C/C++, Perl, Ruby, Java, etc.). - Experience in AI/ML related projects. - **Post-silicon validation** - **Roles** - Post-silicon validation of high-speed SerDes. - SerDes bring-up, functional verification, and performance optimization. - Develop validation methodology and automation scripting to characterize the latest SerDes designs. - Work with design engineers on SerDes silicon issue debug. - Tune and optimize SerDes configuration, and validate SerDes to meet various industrial compliance standards in a PVT environment. - **Preferred skills** - Strong programming/scripting skills (e.g., Python, C/C++, Perl, TCL, etc.) for firmware development, test methodology development, and test automation. - Knowledge of common lab equipment, including BERT, analyzers, oscilloscopes, PNA/VNA, etc. ## Who Are We Looking For - A self-driven individual with a willingness to learn. - Resourceful and passionate about technology. - Willingness to learn with a good attitude. - Willing to work hard. ## Relevant Skillsets - Scripting skills (e.g., Perl, TCL, shell, Python) are beneficial. - Fast learner and ready to solve problems. - Excellent problem-solving and communication skills. - Ability to work collaboratively in a team-oriented environment. ## Academic Credentials - Degree/Master/PhD in Electronics/Electrical/Computer Engineering/Computer Science. ## Placement/Support Letter - Provide a placement/support letter from your school covering the entire internship period. ## Applying to this role This IC Design Exploration Intern role at AMD runs through the firm's own careers portal and expects a CV and cover letter written specifically for the posting, not a portable submission carried across firms. Jorb AI's application agent tailors a CV and cover letter from your background to this posting and tracks the role alongside the rest of your applications. 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