# Early Career CAD Tools Optimisation Engineer (Design Verification)

[Apple](https://www.jorb.ai/firms/apple.md) · London · United Kingdom · [Computer Engineering](https://www.jorb.ai/jobs/computer-engineering.md)

Apple is hiring a Early Career CAD Tools Optimisation Engineer (Design Verification) in London. Posted 2026-03-10; applications close 2026-05-09.

**Apply**: https://jobs.apple.com/en-us/details/200650800/early-career-cad-tools-optimisation-engineer-design-verification

Posted 1mo ago.

## Role details

## Summary

At Apple, new ideas become extraordinary products, services, and customer experiences. We value passion and dedication, and our teams work on innovative technologies that have reinvented entire industries. Our CAD Hardware Tech group focuses on automating processes in designing Apple’s chips, powering devices from Apple Watch and Apple TV to iPhone and iPad. We seek interns and full-time talents who are excited to contribute to groundbreaking methodologies and to help deliver the next Apple product, solving challenges no one has solved yet.

## Description

As a CAD engineer, you will help deliver high-quality infrastructure for automating chip design processes. As chip designs grow larger, there is a growing need to optimize the performance of simulation tools to maximize efficiency and reduce resource requirements (compute time and space). Your work includes developing and deploying new methodologies with vendor and internal teams, and supporting and debugging issues on large-scale simulations.

## Minimum Qualifications

  
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, Computer Science, Software Engineering, or a related field
  
- Experience with working on RTL simulation tools
  
- Foundation in Linux and grid computing systems
  
- Knowledge of scripting languages such as Python or Perl
  
- Strong interpersonal and analytical skills
  
- Ability to work well within a team and be productive under tight schedules

## Preferred Qualifications

  
- Familiarity with Cadence tool chain
  
- Experience with SystemVerilog / Verilog / VHDL
  
- A curiosity about GPU / PMU / CPU / SOC architecture and micro-architecture

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Updated: 2026-04-22
Canonical: https://www.jorb.ai/jobs/69b048831f0126f5b3ddce82