# IC Design Exploration Intern

[AMD](https://www.jorb.ai/firms/amd.md) · Singapore · [Electrical Engineering](https://www.jorb.ai/jobs/electrical-engineering.md)

AMD is hiring a IC Design Exploration Intern in Singapore. Posted 2025-12-29; applications close 2026-02-27.

**Apply**: https://careers.amd.com/careers-home/jobs/76892

Posted 3mo ago.

## Role details

## Overview

As an AMD intern/co-op, you’ll be placed at the epicenter of the AI ecosystem, working alongside experts and industry pioneers. You’ll contribute on meaningful projects, learn new skills, expand your network, and gain real-world experience that impacts millions of end-users worldwide. Whether you’re an undergraduate or a PhD student, your contributions will matter and your experience here can launch your next career steps.

## Location

Singapore

## Internship Details

  
- Criteria: Current students studying at universities based in Singapore
  
- Internship Duration: The internship will begin on either 4 May 2026 or 20 July 2026 and end on 4 December 2026. There is an option to extend the internship, with the extended period concluding on 18 December 2026.

## Role

Intern - IC Design Exploration

## What You Can Expect to Learn

Gain industry experience working on the latest technology process nodes. Learn about pursuing a career in IC design. Because IC design spans multiple disciplines, the application process will help assign you to the most suitable team to fit your strengths.

## Project Overview

Join a dynamic SerDes Technology team and collaborate with teams around the globe. You will explore areas including analog design and implementation, digital design and implementation, functional verification, post-silicon validation, and more. Working alongside engineers across disciplines will help you understand the differences between paths you may pursue after graduation.

## Key Responsibilities

  
- First few weeks
    

      
- Learn about the Singapore Design Team at AMD
      
- Strengthen foundational technical IC design knowledge
      
- Build comfort working independently and in a team across multiple geographical sites
    

  
  
- Next few months
    

      
- Develop soft skills through technical discussions and knowledge-sharing sessions
      
- Consider engineering judgments and trade-offs
      
- Work on projects aligned with your specialization (see Specializations)
    

  
  
- Throughout the internship
    

      
- Participate in company/department events and social activities
      
- Engage in recreation and networking opportunities
    

  

## Specializations

Specializations will be assigned to one of the following tracks. You may explore cross-functional experiences during the program.

### Analog Design

  
- Design and development of high-speed analog and mixed-signal circuits and their auxiliary blocks (112 Gbps and above) in advanced technology nodes (3nm, 7nm)
  
- Use, simulate, and analyze logs from EDA tools; make design trade-offs to meet milestones
  
- Learn the architecture and design of SerDes blocks (transmitter, receiver, PLL, etc.)
  
- Basic scripting and programming (Unix, Python, Perl)
  
- Familiarization with IC design tools (Cadence ADE/Spectre, Synopsys HSPICE/XA, etc.)
  
- Understand IC design flow to implement circuit design and explore cross-functional experiences (RTL/Layout/STA/Verification)

### Analog Layout

  
- Layout implementation in high-speed circuits and their auxiliary blocks (112 Gbps and above) in advanced technology nodes (3nm, 7nm)
  
- Perform LVS and DRC checks; ensure circuit function, performance, and process requirements
  
- Understand Process Design Rules and metal schemes
  
- Basic scripting and programming (Unix, Python, Perl)
  
- Familiarization with IC design tools (Cadence Virtuoso, Calibre, etc.)
  
- Learn IC design flow to implement layout; explore cross-functional experiences (RTL/Circuit/PNR/STA/Verification)

### Analog Timing & Verification

  
- Develop timing models for advanced technology nodes and mixed-signal circuits
  
- Coordinate with design, layout, and integration teams to build constraints and tune design hierarchy for timing models
  
- Develop and update quality-check scripts; release and maintain timing model databases
  
- Evaluate best-in-class EDA tools and flows

### Digital Design

  
- Low-power design explorations; design digital logic blocks in Verilog (RTL)
  
- Develop testbenches and functional verification for digital blocks
  
-  Silicon validation: develop emulation platforms using Python and CocoTB
  
- Post-silicon validation: testing and debugging of block functionality on prototype silicon
  
- Explore next-generation RTL/AI tools; improve RTL quality and productivity

### Digital Implementation

  
- Proficient in UNIX/LINUX environments; use EDA tools (Synopsys Design Compiler, IC Compiler 2, Fusion Compiler)
  
- Implement place-and-route designs across nodes from 3nm to 16nm
  
- Develop plans to synthesize and close timing on complex digital ICs (block/subsystem level)
  
- Design clock structures to meet tight skew; collaborate with Logic, Circuits, DFT & Layout groups to meet timing, area, power, and performance goals
  
- Ensure designs meet DRC/DFM requirements; communicate with global project teams to meet milestones

### Digital Static Timing Analysis

  
- Proficient in UNIX/LINUX; use EDA tools (Synopsys PrimeTime, ICC2, etc.) to develop timing constraints
  
- Simulate and analyze logs/reports; make design trade-offs to meet milestones

### Functional Verification

  
- Verify SerDes and/or Security IP designs; develop testbenches in SystemVerilog/UVM and/or Python-based frameworks
  
- Prepare and manage regressions; debug and resolve design bugs
  
- Perform coverage analysis to ensure all features are verified
  
- Develop automation and hardware acceleration to improve efficiency; explore AI/ML-enabled verification
  
- Explore new verification methodologies to improve quality and productivity

### Post-Silicon Validation

  
- Post-silicon validation of high-speed SerDes; bring-up, verification, and performance optimization
  
- Develop validation methodologies and automation for characterization
  
- Collaborate with design engineers to debug SerDes silicon issues
  
- Tune and optimize SerDes configurations; ensure compliance across PVT environments

## Who We Are Looking For

A self-driven individual with a willingness to learn, resourcefulness, and passion for technology. Must have a positive attitude, be willing to work hard, and enjoy teamwork.

## Relevant Skill Sets

  
- Scripting skills (Perl, TCL, shell, Python) are beneficial
  
- Fast learner with strong problem-solving and communication abilities
  
- Ability to work collaboratively in a team-oriented environment

## Academic Credentials

Bachelor’s, Master’s, or PhD in Electronics/Electrical/Computer Engineering or Computer Science

## Placement Letter

Please ensure you can provide a placement/support letter from your school covering the entire internship period.

## Note

#LI-SP

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Updated: 2026-04-22
Canonical: https://www.jorb.ai/jobs/6976dca1623e3d30419530be
